The present invention relates to data processing, and more specifically, to identification of mistimed forcing of values in the simulation of a design.
Designers typically employ a high level language, such as a hardware description language (HDL), to define the structure and function of a design, such as a design of an integrated circuit. The design files specified in the high level language are then compiled to obtain a simulation model of the design, which is stimulated by a simulation engine with one or more testcases (i.e., a sequence of inputs and associated expected signal values in the design) in order to verify aspects of the design.
Various types of simulation can be utilized to verify designs. Logic or functional simulation, which is often the first type of simulation performed, verifies the logical correctness of the design without regard to timing constraints. Event simulation, which tracks signal changes in the design as events, additionally supports verification in the presence of simple timing information such as signal delays. Cycle simulation, which employs a cycle-accurate model of the design, does not support specification of delays, but instead evaluates every gate in the design every simulation cycle and enables significant performance improvement over event simulation in cases in which, on the whole, signal levels change relatively infrequently.
In functional simulation, forcing a signal in the design to a particular value (commonly referred to “sticking” a signal) is commonly utilized to verify the logical correctness of the design or to determine the response of the design to various combinations of signal values. Because functional simulation is not bound by timing constraints, the practice of forcing signal values does not create any issues as long as the signal value (or combination of signal values) forced on the design is legal. In event simulation and cycle simulation, however, forcing a signal in the design to a particular value can induce an error in the simulation results if the forced signal value is applied at the wrong time relative to other signals in the design, such as clock signals. For example, in the case of flip flops, the output values change at a rising or falling clock edge in event simulators and one simulation cycle after the clock transition in cycle simulators. If the signal value is forced at any other time, the forced change in signal value may cause an unrealistic and therefore erroneous response in the simulation model. Such errors in the simulation results can be difficult to detect.